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CDP1823, CDP1823C
March 1997
128-Word x 8-Bit LSI Static RAM
Description
The CDP1823 and CDP1823C are 128-word by 8-bit CMOS SOS static random-access memories. These memories are compatible with general-purpose microprocessors. The two memories are functionally identical. They differ in that the CDP1823 has a recommended operating voltage range of 4V to 10.5V, and the CDP1823C has a recommended operating voltage range of 4V to 6.5V. The CDP1823 memory has 8 common data input and data output terminals for direct connection to a bidirectional data bus and is operated from a single voltage supply. Five chipselect inputs are provided to simplify memory-system expansion. In order to enable the CDP1823, the chip-select inputs CS2, CS3 and CS5 require a low input signal, and the chipselect inputs CS1 and CS4 require a high input signal. The MRD signal enables all 8 output drivers when in the low state and should be in a high state during a write cycle. After valid data appear at the output, the address inputs may be changed immediately. Output data will be valid until either the MRD signal goes high, the device is deselected, or tAA (access time) after address changes.
Features
* Fast Access Time - VDD = 5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450ns - VDD = 10V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250ns * Common Data Inputs and Outputs * Multiple Chip Select Inputs to Simplify Memory System Expansion
Ordering Information
5V CDP1823CE CDP1823CD CDP1823CDX 10V CDP1823E CDP1823D PACKAGE PDIP SBDIP Burn-In TEMP. RANGE PKG. NO.
-40oC to +85oC E24.6 -40oC to +85oC D24.6 D24.6
Pinout
CDP1823, CDP1823C (PDIP, SBDIP) TOP VIEW
BUS 0 BUS 1 BUS 2 BUS 3 BUS 4 BUS 5 BUS 6 BUS 7 CS1
1 2 3 4 5 6 7 8 9
24 VDD 23 MA0 22 MA1 21 MA2 20 MA3 19 MA4 18 MA5 17 MA6 16 MWR 15 MRD 14 CS5 13 CS4
CS2 10 CS3 11 VSS 12
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
1198.2
6-24
CDP1823, CDP1823C
OPERATIONAL MODES FUNCTION Read Write Stand-By (Active) Not Selected MRD 0 1 1 X X X X X MWR X 0 1 X X X X X CS1 1 1 1 0 X X X X CS2 0 0 0 X 1 X X X CS3 0 0 0 X X 1 X X CS4 1 1 1 X X X 0 X CS5 0 0 0 X X X X 1 BUS TERMINAL STATE Storage State of Addressed Word Input High-Impedance High Impedance High Impedance High Impedance High Impedance High Impedance High Impedance
Logic 1 = High, Logic 0 = Low, X = Don't Care
6-25
CDP1823, CDP1823C
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) (All Voltages Referenced to VSS Terminal) CDP1823 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V CDP1823C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .10mA Operating Temperature Range (TA) Package Type D . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC Package Type E . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
Thermal Information
Thermal Resistance (Typical) JA (oC/W) JC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 60 N/A SBDIP Package . . . . . . . . . . . . . . . . . . 60 17 Maximum Storage Temperature Range (TSTG) . . .-65oC to +150oC Maximum Junction Temperature Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150oC Maximum Lead Temperature (During Soldering) . . . . . . . . . . 300oC
Recommended Operating Conditions
At TA = Full Package Temperature Range. For maximum reliability, operating conditions should be selected so that operation is always within the following ranges: LIMITS CDP1823D CDP1823CD MAX 10.5 VDD MIN 4 VSS MAX 6.5 VDD UNITS V V
PARAMETER Supply Voltage Range Recommended Input Voltage Range
MIN 4 VSS
Static Electrical Specifications
At TA = -40oC to +85oC, Except as Noted: CONDITIONS CDP1823 LIMITS CDP1823C MAX 500 1000 0.1 0.1 1.5 3 5 10 8 16 5 10 7.5 15 MIN 2 -1 4.9 3.5 (NOTE 1) TYP 4 -2 0 5 4 5 10 MAX 500 0.1 1.5 5 8 5 7.5 15 UNITS A A mA mA mA mA V V V V V V V V A A mA mA A A pF pF
PARAMETER Quiescent Device Current Output Low (Sink) Current Output High (Source) Current Output Voltage Low-Level Output Voltage High-Level Input Low Voltage
SYMBOL IDD IOL IOH VOL VOH VIL VIH IIN IDD1 IOUT CIN COUT
VO (V) 0.4 0.5 4.6 9.5 0.5, 4.5 0.5, 9.5
VIN (V) 0, 5 0, 10 0, 5 0, 10 0, 5 0, 10 0, 5 0, 10 0, 5 0, 10 0, 5 0, 10 0, 5 0, 10 0, 5 0, 10 -
VDD (V) 5 10 5 10 5 10 5 10 5 10 5 10 5 10 5 10 5 10 5 10 -
MIN 2 4.5 -1 -2.2 4.9 9.9 3.5 7 -
(NOTE 1) TYP 4 9 -2 -4.4 0 0 5 10 4 8 5 10
Input High Voltage
0.5, 9.5 0.5, 9.5
Input Leakage Current
Any Input 0, 5 0, 10 -
Operating Current (Note 2) Three-State Output Leakage Current Input Capacitance Output Capacitance NOTES:
1. Typical values are for TA = +25oC and nominal VDD. 2. Outputs open circuited; Cycle time = 1s.
6-26
CDP1823, CDP1823C
Dynamic Electrical Specifications
At TA = -40 to +85oC, VDD 5%, tR, tF = 20ns, CL = 100pF LIMITS CDP1823 VDD (V) (NOTE 2) MIN (NOTE 1) TYP (NOTE 2) MIN CDP1823C (NOTE 1) TYP
PARAMETER Read Cycle (See Figure 1) Access Time From Address Change Access Time From Chip Select MRD to Output Active
SYMBOL
MAX
MAX
UNITS
tAA
5 10
25 15
275 150 150 100 150 100 50 25
450 250 250 150 250 150 75 40
25 -
275 150 150 50 -
450 250 250 75 -
ns ns ns ns ns ns ns ns
tDOA
5 10
tAM
5 10
Data Hold Time After Read
tDOH
5 10
NOTES: 1. Typical values are at TA = 25oC and nominal voltage. 2. Time required by a limit device to allow for the indicated function.
+
tAA ADDRESS
tAM MRD
CS2, CS3, CS5 tDOA CS1, CS4 tDOH 90% DATA OUT HIGH IMPEDANCE VALID DATA 10%
NOTE: 1. MWR is high during read operation. Timing measurement reference is 0.5 VDD. FIGURE 1. READ CYCLE TIMING DIAGRAM
6-27
CDP1823, CDP1823C
Dynamic Electrical Specifications
At TA = -40 to +85oC, VDD 5%, t R, tF = 20ns, CL = 100pF LIMITS CDP1823 VDD (V) (NOTE 2) MIN (NOTE 1) TYP CDP1823C (NOTE 2) (NOTE 1) MIN TYP
PARAMETER Write Cycle (See Figure 2) Write Recovery
SYMBOL
MAX
MAX
UNITS
tWR
5 10
75 50 400 225 200 100 125 75 100 75 75 50
-
-
75 400 200 125 100 75 -
-
-
ns ns ns ns ns ns ns ns ns ns ns ns
Write Cycle
tWC
5 10
Write Pulse Width
tWRW
5 10
Address Setup Time
tAS
5 10
Data Setup Time
tDS
5 10
Data Hold Time From MWR
tDH
5 10
NOTES: 1. Typical values are at TA = 25oC and nominal voltage. 2. Time required by a limit device to allow for the indicated function.
tWC tAS ADDRESS
tWR CS1, CS4
CS2, CS3, CS5
MWR
tWRW tDS tDH
BUS 0-7
VALID DATA
NOTE: 1. MRD must be high during write operation. FIGURE 2. WRITE CYCLE TIMING DIAGRAM
6-28
CDP1823, CDP1823C
Data Retention Specifications
At TA = -40 to +85oC, see Figure 3 LIMITS TEST CONDITIONS VDR (V) VDR 2 tRC tR, tF 2 VDD (V) 5 10 5 10 5 CDP1823 (NOTE 1) TYP 1.5 30 CDP1823C (NOTE 1) TYP 1.5 30 -
PARAMETER Minimum Data Retention Voltage,
MIN 600 300 600 300 1
MAX 2 100 -
MIN 600 600 1
MAX 2 100 -
UNITS V A ns ns ns ns s
Data Retention Quiescent Current, IDD Chip Deselect to Data Retention Time tCDR Recovery to Normal Operation Time VDD to VDR Rise and Fall Time NOTE: Typical values are for TA = 25oC and nominal VDD.
DATA RETENTION MODE VDD 0.95 VDD VDR tCDR CS1 VIH VIL tF tR tRC VIH VIL 0.95 VDD
FIGURE 3. LOW VDD DATA RETENTION TIMING WAVEFORMS
MA0 MA1 MA2 MA3 BUFFER AND DECODER 16 x 8 x 8 STORAGE ARRAY
MA4 MA5 MA6 BUFFER DECODER
MRD MWR CS1 CS2 CS3 CS4 CS5
CONTROL
BUS 0-7
FIGURE 4. FUNCTIONAL DIAGRAM
6-29
CDP1823, CDP1823C
CPU/ROM SYSTEM
RAM INTERFACE
RAM SYSTEM
ADDRESS
MA0 - MA7 TPA MRD MWR CPU CDP1802
MA0- MA7 TPA MRD
MA0 - MA6
MRD MWR
ROM CDP1833 CE0 CS
RAM CDP1823
BUS0 - BUS7
BUS0 - BUS7
BUS0 - BUS7
DATA
FIGURE 5. CDP1823 (128 x 8) MINIMUM SYSTEM (128 x 8)
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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Sales Office Headquarters
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6-30

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